One question:

When two cores have the same cacheline shared and are trying to write to it.

Core 0 may be the first and mark the cacheline Modified and marks the Core 1 cacheline as Invalid. When Core 1 then tries to write and sees the cacheline invalid, does it have to reload the cacheline AND redo the computation with the new cacheline values? Or just reload and write?

Just reload and repeat write. There is no computation to perform because it is just the write.

Ah ofcourse, I was thinking about a whole cacheline being written. But only a register value will be written to the cacheline.

Thanks for jumpstarting my memory...