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Jason
195 posts
Imporant CPU architectural designs programmers should know about?
Edited by Jason on
Nowadays we all here about he importance of data locality when trying to create a performant program. Of course this is due to a CPU's utilization of cache memory. What I'm curious about is if there are other major CPU mechanisms the programmer should be aware of besides the cache? I know CPU's also have plenty of other architectural designs to help increase instruction completion rate, just wansn't sure which of those mechanisms can also be significantly influenced by program design and not already heavily optimized for by the compiler.
Martin Fouilleul
38 posts
PhD student at Ircam, doing research on programming languages for temporal interaction. Former sound engineer and computer music designer.
Imporant CPU architectural designs programmers should know about?
I found this post from Fabian Giesen very interesting on pipelined architectures and instruction-level parallelism : https://fgiesen.wordpress.com/201...-introduction-to-dataflow-graphs/
Jason
195 posts
Imporant CPU architectural designs programmers should know about?
Thank you for the link! Definitely has some interesting ideas. Though not gonna lie, its hard to digest everything he talks about. I'll have to read it over a few times to really grasp the concepts well.